<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Qualcomm · LLMobile.news</title><link>https://llmobile.news/companies/qualcomm/</link><description>A concise news ticker covering AI on mobile devices, local models, apps and hardware.</description><language>en-GB</language><atom:link href="https://llmobile.news/companies/qualcomm/index.xml" rel="self" type="application/rss+xml"/><item><title>ASUS announces Ascent QN10, a mini PC with Snapdragon X2 Elite and an 80 TOPS NPU</title><link>https://llmobile.news/ticker/asus-ascent-qn10/</link><guid isPermaLink="true">https://llmobile.news/ticker/asus-ascent-qn10/</guid><pubDate>Wed, 16 Sep 2026 00:00:00 +0200</pubDate><description>ASUS has announced the Ascent QN10, a mini PC built on the Snapdragon X2 Elite platform with an 18-core Qualcomm Oryon CPU and a Hexagon NPU rated at up to 80 TOPS. The company calls it the first AI mini PC with an 80 TOPS NPU and says it exceeds the Copilot+ PC requirements. The chassis measures under 0.7 liters, which ASUS puts at 86% smaller than a conventional 5-liter desktop, and the Adreno GPU is 2.3 times faster than in the previous generation.
According to ASUS, the NPU is meant for local LLM inferencing, real-time translation, content generation, video enhancement and AI assistants. Developers can reach the Qualcomm AI Hub, which offers 175+ pre-optimized models and supports bringing their own models and data. The PC also runs agent frameworks such as OpenClaw and Hermes Agent, and ASUS describes a hybrid setup that routes workloads between cloud LLM APIs and the local NPU.
Guru3d lists 16 GB or 32 GB of soldered LPDDR5X, two M.2 slots, Windows 11 on Arm and a 130 x 130 x 40 mm body, and reports that no price has been announced. The Gadgeteer names $1,349 for 16 GB with 512 GB of storage and $1,699 for 32 GB. Connectivity includes WiFi 7 and Bluetooth 6.0, and security comes from fTPM 2.0 and the Microsoft Pluton processor.
Source: https://press.asus.com/news/press-releases/asus-ascent-qn10-mini-pc-snapdragon-x2-elite/
Read the article: https://llmobile.news/ticker/asus-ascent-qn10/</description><category>Chips</category><category>NPU</category><category>Developer tools</category></item><item><title>Qualcomm teases next-gen Hexagon NPU ahead of Snapdragon Summit 2026</title><link>https://llmobile.news/ticker/qualcomm-hexagon-npu-agentic-ai/</link><guid isPermaLink="true">https://llmobile.news/ticker/qualcomm-hexagon-npu-agentic-ai/</guid><pubDate>Thu, 10 Sep 2026 00:00:00 +0200</pubDate><description>Qualcomm has teased its next-generation Hexagon NPU ahead of Snapdragon Summit 2026 (Sep 22–24), detailing an architecture redesigned around persistent on-device AI agents rather than single-pass inference. The full platform — widely expected to be a Snapdragon 8 Elite Gen 6 — will be formally announced at Summit. Qualcomm has not yet named the chip or provided absolute figures for memory capacity or NPU throughput.
Two architectural changes stand out. The Element Accelerator is a new block inside the Hexagon NPU dedicated to transformer operations, working alongside the existing scalar, vector and matrix units. It targets the compute patterns that modern generative and agentic models use. A 50% larger shared memory subsystem inside the NPU keeps more model state, activations and intermediate tensors on-chip, reducing trips to external LPDDR — a move aimed at the memory wall that has long bottlenecked mobile AI, especially with long context windows.
The NPU also prepares for Mixture-of-Experts (MoE) models. The company cites a 30-billion-parameter MoE that activates only about 3B parameters per token, keeping tens of billions available without the bandwidth cost of dense models. This is paired with flash-to-memory expert management and caching to load the right experts from storage. INT2, INT4, INT8, FP8 and FP16 precision are supported, and the new platform delivers up to 50% higher prefill performance for INT4 models, faster decoding throughput and enhanced speculative decoding.
The design targets always-running AI with long-context reasoning and low-latency action loops, with the CPU handling routing and orchestration of multi-step workloads while Hexagon accelerates the heavy lifting. Adreno handles AI-accelerated graphics rendering and a new Neural Fusion layer extends AI acceleration into gaming. Whether this actually delivers faster, more capable local assistants depends on finished devices — several critical figures (absolute memory size, power consumption, real-world benchmarks) remain undisclosed. The full picture comes at Summit in two weeks.
Source: https://www.qualcomm.com/news/onq/2026/09/hexagon-npu-agentic-ai-architecture
Read the article: https://llmobile.news/ticker/qualcomm-hexagon-npu-agentic-ai/</description><category>NPU</category><category>Qualcomm</category><category>Agentic AI</category><category>MoE</category></item><item><title>NPUs lead LLM prefill, CPUs lead decoding on Snapdragon phones</title><link>https://llmobile.news/ticker/mobile-npu-llm-inference-study/</link><guid isPermaLink="true">https://llmobile.news/ticker/mobile-npu-llm-inference-study/</guid><pubDate>Mon, 06 Jul 2026 00:00:00 +0200</pubDate><description>A team of researchers has published a cross-layer measurement study of mobile LLM inference titled &amp;amp;ldquo;Is Your NPU Ready for LLMs?&amp;amp;rdquo;. It covers five frameworks, llama.cpp, MNN, MLC-LLM, MLLM and Qualcomm&amp;amp;rsquo;s GENIE, on CPU, GPU and NPU backends. The study finds that framework-induced performance gaps grow on NPUs and reach up to 10x.
The tests ran on four Snapdragon phones, the Xiaomi 17, OnePlus 15, Xiaomi 15 and Xiaomi 14, with Llama 3.2 1B and 3B, Qwen 2.5 1.5B and 7B and Phi 3.5 3.8B, mostly with 4-bit weights. At a 256-token context, GENIE on the NPU reaches 1,463.7 tok/s in prefill against 115.1 tok/s for llama.cpp. In decoding the order flips, with the CPU at about 50 to 76 tok/s and the NPU at about 10 to 34 tok/s. The authors attribute this to NPUs preferring large, fixed-shape workloads, which conflicts with the small, dynamic kernels of decoding.
For energy, the team built PowerBench, a lightweight C++ library that maps PMIC power zones to CPU, GPU and NPU for backend-specific attribution. They report that suboptimal configurations waste up to 40% of energy and that a tuned setup cuts NPU energy by up to 54.8%. The recommended settings are a 20 μs RPC polling interval, an NPU sleep latency of 65535 μs, the CPU at its lowest frequency and full-graph offloading with QNN.
Source: https://arxiv.org/abs/2607.05475
Read the article: https://llmobile.news/ticker/mobile-npu-llm-inference-study/</description><category>Research</category><category>Benchmarks</category><category>NPU</category><category>Android</category><category>Runtimes</category></item></channel></rss>