https://llmobile.news/tags/chips/A concise news ticker covering AI on mobile devices, local models, apps and hardware.en-GBhttps://llmobile.news/ticker/qualcomm-amon-100b-models-phones-2028/https://llmobile.news/ticker/qualcomm-amon-100b-models-phones-2028/Thu, 08 Oct 2026 15:30:00 +0200Qualcomm chief executive Cristiano Amon says AI companies have asked his company to make phones capable of running at least a 100-billion-parameter model by 2028, with the model active almost continuously. Amon made the remarks on Alex Heath’s Sources podcast, recorded live at Qualcomm’s Snapdragon Summit in Maui, though he declined to name the companies behind the request. He said they want a model “running kind of all the time”, according to a transcription by The Next Web. Some of the companies at the forefront of AI are telling Qualcomm, ‘By 2028, I need to make sure that I have the ability to run at least a hundred billion parameter model into a phone.’ AI companies are also starting to build their own handsets, Amon said, naming ByteDance’s Doubao phone, manufactured by Nubia, as an example from China and adding that more are coming. Heath pointed out that personal agents such as Muse and Grok Bot drive browsers on virtual machines in the cloud rather than on the phone. Amon answered that some of that work will stay in data centers while some of it has to happen on the device. Humans are not going to go travel to a data center, ring the bell and say, ‘Give me some AI.’ Amon likened the moment to the early iPhone, when the applications that later defined the platform did not yet exist. He said “The smartphone was defined by the third-party applications,” and he expects agents to play that role on the next generation of phones. The launch of OpenClaw made the idea of an AI-first smartphone concrete for him, he said, describing an agent that plans, routes tasks and acts on the user’s behalf. Qualcomm’s current flagship silicon sits below that 2028 target. The company announced the Snapdragon 8 Elite Extreme Gen 6 at the same summit, and Computerbase reports that the Extreme variant gets 50 percent more dedicated NPU memory, which Qualcomm says prepares it for mixture-of-experts models, where only part of the model is active per token — the example given is a 30-billion-parameter model with roughly 3 billion active. The interview does not say how much memory or storage a 100-billion-parameter model would need on a phone. Memory prices have risen five to six times, Amon said, and the smartphone market is down 20% this year as a result. He said buyers are putting off upgrades rather than losing interest, saying “It’s not a demand problem” and pointing to pent-up demand. Amon put annual phone sales at about 1.2 billion units and said the market remains smaller than it was in 2019. Source: https://sources.news/p/qualcomm-ceo-ai-phone Read the article: https://llmobile.news/ticker/qualcomm-amon-100b-models-phones-2028/ChipsAgentsMemoryBusinesshttps://llmobile.news/ticker/snapdragon-x2-agentic-pc/https://llmobile.news/ticker/snapdragon-x2-agentic-pc/Thu, 24 Sep 2026 08:50:48 +0200At Snapdragon Summit 2026 in Maui, Qualcomm framed the Snapdragon X2 Elite and X2 Elite Extreme, the laptop chips it launched a year earlier and has shipped since spring 2026, as the hardware for “agentic” PCs that run AI agents locally rather than answering single prompts. Qualcomm says updated configurations of the Hexagon NPU now reach up to 85 TOPS, up from the 80 TOPS specified at launch, on a platform with 228 GB/s of memory bandwidth. The company also claims up to twice the tokens per second of the first-generation Snapdragon X Elite, 450 supported on-device models, and models up to 30 billion parameters running locally with a 200,000-token context window. Much of that agent support runs through GenieX, an open-source, BSD-3-Clause inference runtime Qualcomm released in developer preview after acquiring Nexa AI earlier in 2026. GenieX accepts GGUF models from Hugging Face through llama.cpp, precompiled bundles from Qualcomm AI Hub, or a developer’s own model, and dispatches them across the Hexagon NPU, Adreno GPU or CPU. Developers reach it through a local server, a CLI, a Python SDK, Docker or Linux builds, or an Android interface. Qualcomm says AnythingLLM and LLMWare already run natively on Snapdragon X2, while OpenClaw runs directly on top of GenieX. In its compute keynote at the summit, Qualcomm said its Concierge demo uses this dispatch model for tiered routing: Clairvoyance AI sends chat and simple requests to a 3B model, light tool use to a 9B model, and high-compute agentic work to a 27B model, all served locally on the Hexagon NPU through GenieX. These figures come from the keynote presentation rather than a published spec sheet, and Qualcomm did not disclose which 27B model it used, its quantization, the RAM configuration, context length, tokens per second or sustained thermals for that demo, so the on-device feasibility of the largest tier remains unverified. One demo Qualcomm calls Creator pairs AnythingLLM with ON1 Photo RAW to search, organize and generate from a photo library using plain-language requests instead of manual tagging or folders. Qualcomm showed two further local-agent demos built with partners: a podcast assistant that uses Deepgram for real-time transcription, and a security agent built with Pokee and Halo for continuous monitoring and deepfake detection. Running large models locally on a laptop currently means choosing between different platform approaches: Apple pairs its GPU with a large pool of unified memory, AMD’s Strix Halo chips do the same, Nvidia’s laptop GPUs run faster but are limited by fixed VRAM, and Qualcomm’s Snapdragon X2 leans on NPU-driven inference backed by its platform’s 228 GB/s of memory bandwidth rather than a larger GPU. Qualcomm also published an early developer preview of Linux for Snapdragon X2 laptops, making Linux a third operating system option alongside Windows and Google’s Googlebook platform. The preview boots over UEFI, supports USB and PCIe, and drives the display and GPU through the open-source Freedreno, Turnip and Rusticl stack, while the Hexagon NPU is reachable through the FastRPC driver, running on a Debian 13 userspace with a custom-built kernel that developers have to compile themselves. Qualcomm targets foundational Debian support by the end of 2026, with Ubuntu certification and Linux laptops from HP, ASUS and HUMAIN planned for the first half of 2027. GenieX and the Linux preview are both available to developers now, though neither is consumer-ready, Microsoft’s Windows 11 26H1 update will be exclusive to Snapdragon X2 PCs, and the chips themselves have been shipping in laptops since spring 2026. Source: https://www.qualcomm.com/news/onq/2026/09/snapdragon-summit-agentic-ai-pcs-linux Read the article: https://llmobile.news/ticker/snapdragon-x2-agentic-pc/ChipsNPUDeveloper toolsOpen sourcehttps://llmobile.news/ticker/apple-mac-mini-mac-studio-m5/https://llmobile.news/ticker/apple-mac-mini-mac-studio-m5/Wed, 23 Sep 2026 09:35:00 +0200Apple has started shipping an updated Mac mini and a new Mac Studio topping out at the M5 Ultra chip. Apple says the configuration lets “AI researchers run enormous LLMs entirely on device,” citing up to 512GB of unified memory and 1.2TB/s of memory bandwidth on the top Mac Studio. The Mac mini starts with a 12-core M6 chip, a 12-core GPU with Neural Accelerators in every core, and a dual 16-core Neural Engine, running 16GB of unified memory at up to 170GB/s of bandwidth. A Mac mini with the M5 Pro chip steps up to an 18-core CPU, a 20-core GPU and up to 64GB of memory at 307GB/s. Apple prices the M6 Mac mini from $899 and the M5 Pro model from $1,699. The Mac Studio comes in M5 Max and M5 Ultra configurations, with the Max offering an 18-core CPU and up to a 40-core GPU with up to 128GB of unified memory, starting at $2,499. The M5 Ultra model reaches a 36-core CPU, an 80-core GPU and up to 512GB of memory, starting at $5,499. Apple says Thunderbolt 5 with Remote Direct Memory Access lets multiple Mac Studio systems cluster together, giving up to 3x faster performance for distributed AI inference compared with a single system. The new Mac mini and Mac Studio models became available on September 22, running macOS 27 with Apple Intelligence and Siri AI features. Apple also offers leasing plans starting at $48.99 a month for the M5 Max Mac Studio and $110.10 a month for the M5 Ultra model over 36 months. Source: https://www.apple.com/newsroom/2026/09/the-new-mac-mini-and-mac-studio-are-available-today/ Read the article: https://llmobile.news/ticker/apple-mac-mini-mac-studio-m5/ChipsMemoryhttps://llmobile.news/ticker/mediatek-dimensity-cx-c10-max/https://llmobile.news/ticker/mediatek-dimensity-cx-c10-max/Wed, 23 Sep 2026 09:25:00 +0200MediaTek has launched the Dimensity CX C10 Max, the first chip in a new “Compute Experiences” line built for Googlebook, Google’s laptop category, alongside chips from Intel and Qualcomm. Built on a 3nm process, it pairs an eight-core Arm CPU and an 11-core GPU with MediaTek’s NPU 890, which the company rates at up to 55 TOPS. The CPU uses an all-big-core layout with one Cortex-X925 core at up to 3.73 GHz, three Cortex-X4 cores and four Cortex-A720 cores, backed by 12 MB of L3 cache and 10 MB of system-level cache, according to MediaTek’s product page. The 11-core Arm Immortalis-G925 GPU supports LPDDR5X memory at up to 9,600 Mbps and UFS 4.0 storage. MediaTek pitches the chip for on-device agentic AI, including multimodal, real-time workflows such as live transcription and summarization that it says run locally without sending data to the cloud. A separate Imagiq 1090 image processor supports sensors up to 32MP. Tom’s Hardware reports that the C10 Max’s CPU, GPU and NPU configuration is nearly identical to the Kompanio Ultra 910 already used in Chromebook Plus devices. The outlet notes the Cortex-X925 clock rises only from 3.62 GHz to 3.73 GHz, LPDDR5X speed from 8,533 to 9,600 Mbps, and NPU throughput from 50 to 55 TOPS, despite MediaTek’s framing of the chip as elevating its computing portfolio. Vince Hu, MediaTek’s senior vice president, said the chip is “designed for the next wave of intelligent computing, combining flagship performance and power-efficient processing.” MediaTek’s release names no pricing or launch date for Googlebook devices using the C10 Max, saying only that it enables thinner, lighter, fanless laptop designs with all-day battery life. Source: https://www.mediatek.com/press-room/mediatek-dimensity-cx-c10-max-offers-flagship-performance-to-a-new-era-of-ai-first-laptops Read the article: https://llmobile.news/ticker/mediatek-dimensity-cx-c10-max/ChipsNPUAndroidhttps://llmobile.news/ticker/snapdragon-8-elite-extreme-gen-6/https://llmobile.news/ticker/snapdragon-8-elite-extreme-gen-6/Wed, 23 Sep 2026 09:15:00 +0200Qualcomm has announced two flagship mobile chips, the Snapdragon 8 Elite Gen 6 and a pricier Snapdragon 8 Elite Extreme Gen 6, both built on a 2nm process and positioned around what the company calls the “agentic AI” era. The Extreme model’s Hexagon NPU carries 50% more shared memory than the standard chip, which lets it run mixture-of-experts models, where only part of the model activates per token, with more than 30 billion parameters directly on a phone, according to Computerbase. Qualcomm calls the chips’ Oryon prime cores, which reach 5.0 GHz, the first smartphone CPU cores to cross that clock speed, according to Tech Advisor. The fourth-generation Oryon CPU pairs two prime cores at 5.0 GHz with six performance cores at 4.0 GHz, sharing a single 16 MB cache pool that replaces the previous generation’s split 12+12 MB layout. Qualcomm claims 10% higher CPU performance on the Elite and 13% on the Extreme. The Adreno GPU clock rises to 1.45 GHz from 1.2 GHz, with reported gains of 35% and 44%, and the Extreme adds Matrix Cores for a feature called Adreno Neural Fusion, which handles AI-based upscaling and frame generation that the standard Elite lacks, according to Xenospectrum. The Hexagon NPU keeps the same 12 scalar and 8 vector units as the previous generation but adds a new tensor unit and a redesigned Element Accelerator for element-wise tensor operations. Xenospectrum reports NPU performance gains of 35% on the Extreme and 14% on the standard Elite, with efficiency improvements of 33% and 20% respectively. Qualcomm frames the extra NPU memory and efficiency around “everyday agents” that respond faster, adapt to the user and learn throughout the day, with an enhanced Sensing Hub handling always-on, on-device voice processing. Honor, Motorola, OnePlus, Oppo, Vivo and Xiaomi are confirmed adopters, while Samsung was notably absent from Qualcomm’s list. Tech Advisor names the Motorola Signature 27 as the first confirmed device. The chips also add support for LPDDR6-10600 memory alongside existing LPDDR5X-10600, and UFS 5.0 storage that doubles per-lane transfer rates to 46.4 Gbit/s, according to Computerbase. Qualcomm's own figures for the Snapdragon 8 Elite Extreme Gen 6, including the Element Accelerator's 30B+ parameter MoE support and the 5.0 GHz Oryon CPU. Credit: Qualcomm Source: https://www.qualcomm.com/news/releases/2026/09/snapdragon-leads-the-agentic-ai-age-with-two-of-the-world-s-fast Read the article: https://llmobile.news/ticker/snapdragon-8-elite-extreme-gen-6/ChipsNPUAndroidhttps://llmobile.news/ticker/googlebook-snapdragon-x-elite/https://llmobile.news/ticker/googlebook-snapdragon-x-elite/Tue, 22 Sep 2026 12:41:09 +0200Qualcomm says the Snapdragon X Elite powers the first Googlebook laptops, Google’s new laptop category built around its Gemini Intelligence features. According to Qualcomm’s release, the chip provides all-day battery life, NPU-powered tools and connectivity with Android phones. Google’s own announcement says Googlebook runs millions of Android apps, many of them optimized for large screens, mouse and keyboard input. The Snapdragon models are the Dell XPS Googlebook 13 and the HP Googlebook 14. The Snapdragon X Elite has 12 Oryon CPU cores and a Hexagon NPU rated at 45 TOPS, according to Tom’s Hardware, which Qualcomm has called the fastest NPU for laptops. Dell says the XPS Googlebook runs its local Gemini Intelligence features, including Magic Pointer and Rambler, on that NPU. Magic Pointer brings up Gemini when the user wiggles the cursor over something on screen, and features such as Cast My Apps and Continue On hand tasks and phone apps over between an Android phone and the laptop. Pre-orders are open, with devices reaching US shelves on October 4 and Canada, the UK, Ireland, France, Germany and Australia a day later, according to Google. Dell prices the XPS Googlebook 13 with 16 GB of RAM and 512 GB of storage starting at $999, while HP prices the Googlebook 14 starting at $1,199.99. Acer, ASUS and Lenovo also build Googlebooks, and Google puts the lineup’s entry price at $899. Google's own lineup image for the Googlebook launch, showing devices from several of its five hardware partners. Credit: Google Source: https://www.qualcomm.com/news/releases/2026/09/snapdragon-x-series-powers-googlebook--the-first-laptops-designe Read the article: https://llmobile.news/ticker/googlebook-snapdragon-x-elite/ChipsNPUAndroidhttps://llmobile.news/ticker/arm-mali-g2-ultra-nx/https://llmobile.news/ticker/arm-mali-g2-ultra-nx/Fri, 18 Sep 2026 20:26:52 +0200Arm has introduced the Mali G2-Ultra NX, a smartphone GPU that places dedicated neural accelerators inside each shader core. The accelerators reuse the GPU’s memory system, coherent caches and control structures, support INT8 and INT16 processing and include hardware-accelerated optical flow for motion estimation. Arm calls it the first AI-native Mali GPU and positions the accelerators for neural graphics at 1 W. The GPU is part of the Arm CSS for Mobile 2 platform. The GPU reaches up to 24% higher benchmark performance than the previous generation and 14% higher performance in non-AI gaming workloads, Arm says. Its neural graphics features are Neural Super Sampling, which reconstructs a higher-resolution image from a lower-resolution render, Neural Frame Rate Upscaling, which generates intermediate frames, and Neural Super Sampling and Denoising, which combines upscaling with denoising for ray-traced scenes. Arm says frame rate upscaling supports up to 120 FPS for longer gaming sessions. In its Neural Dawn demo, Arm reports up to 4x higher performance efficiency and up to 70% lower external memory traffic. Arm's overview slide for the Mali G2-Ultra NX Credit: Arm Arm's diagram of how Neural Frame Rate Upscaling builds an intermediate frame Credit: Arm The new execution engine is the largest update to the Mali instruction set architecture in seven generations, Arm says, with up to 2x more registers per warp. The third-generation hardware ray tracing unit adds support for Opacity Micromaps, which handle complex transparent geometry. Arm reports up to 13% lower DRAM traffic on ray tracing benchmarks, a 30% higher frame rate and up to 70% less ray tracing work in a scene from Moku’s Central Garden. For developers, Arm offers the Arm Neural Graphics Development Kit with machine learning extensions for Vulkan, plug-ins for Unreal Engine, an SDK for custom engines and tools for profiling, training and model optimization. Arm names integrations with Tencent Games Central Tech’s Magic Dawn engine, Unity China’s Tuanjie Engine and Unreal Engine MegaLights. Keli Zhou, engine lead for Where Winds Meet, says the game will be among the first to bring Arm Neural Technology to players. Arm’s post names no launch dates for devices with the GPU. Source: https://newsroom.arm.com/blog/arm-mali-g2-ultra-nx-ai-native-mobile-graphics Read the article: https://llmobile.news/ticker/arm-mali-g2-ultra-nx/ChipsAndroidhttps://llmobile.news/ticker/arm-css-for-mobile-2/https://llmobile.news/ticker/arm-css-for-mobile-2/Fri, 18 Sep 2026 20:26:52 +0200Arm has introduced Arm CSS for Mobile 2, a compute platform for smartphone chips that combines the C2 CPU cluster, the Mali G2-Ultra NX GPU and the SI L2 system interconnect. The C2 cluster pairs C2-Ultra and C2-Pro CPUs with two SME2 units, the Scalable Matrix Extension 2 that speeds up matrix math for AI on the CPU. Arm says this doubles the SME2 capability of the previous-generation configuration and reports up to 1.7x performance across the latest AI models. The cluster delivers up to 15% higher single-thread performance, 15% faster web browsing, 12% faster app launch and 12% higher multi-thread performance, Arm reports. For AI, it cites a peak uplift of up to 70% in selected tasks. Its slide compares speech, personal memory retrieval and prefill, the phase where a model reads the prompt, against the C1-Ultra with SME2. In a representative agentic workflow covering speech processing, memory retrieval, reasoning, app execution and web browsing, the C2-Ultra with two SME2 units finishes 24% faster than the previous generation, according to Arm. Arm's own comparison of the C2-Ultra with the C1-Ultra, with the AI tasks measured against the C1-Ultra with SME2 Credit: Arm The example flagship configuration in Arm’s slides has two C2-Ultra and six C2-Pro cores. The Mali G2-Ultra NX GPU integrates neural accelerators into its shader cores and adds a new execution engine and a third-generation ray tracing unit for neural graphics. Arm says the SI L2 interconnect provides lower-latency access, higher bandwidth, coherency and quality-of-service controls for CPU, GPU and other resources working at the same time. Partners can use each component on its own or combine them with custom and third-party IP. Arm's slide for the C2-Ultra CPU with an example flagship cluster layout Credit: Arm On the software side, Arm lists KleidiAI, its optimized libraries for Arm CPUs including SME2 paths, plus integrations with common AI frameworks. The Arm AI Portal offers validated models with performance and accuracy data, code examples and deployment resources, and the Arm MCP Server connects them to agentic development tools. vivo says it is bringing Arm Neural Technology to its latest flagship smartphones built on the platform, aimed at mobile gaming. Arm’s post names no launch dates for devices with CSS for Mobile 2. Source: https://newsroom.arm.com/blog/arm-css-for-mobile-2-and-c2-cpu-cluster Read the article: https://llmobile.news/ticker/arm-css-for-mobile-2/ChipsAndroidhttps://llmobile.news/ticker/arm-create-china-2026/https://llmobile.news/ticker/arm-create-china-2026/Fri, 18 Sep 2026 20:26:52 +0200Arm has published five developer takeaways from Arm Create, its developer events in Shanghai and Shenzhen. Two of them concern on-device AI. Arm says model choice starts with the workload and not with model size alone, and that developers should decide which parts of an application stay on the device, which run on nearby edge infrastructure and which need the cloud. The Shenzhen panel included Alibaba Qwen, ModelBest, Tencent Hunyuan and Ultralytics. In the Shanghai keynote, Shantu Roy, Arm’s VP of Developer Relations, discussed the Arm AI Portal. Arm says the portal lists models validated and optimized for Arm-based platforms, together with performance data for specific targets, code and deployment workflows. Coding agents can reach the same information through the Arm MCP Server. The recap shows the portal’s evaluation of Qwen3-TTS 0.6B Custom Voice, a multilingual streaming text-to-speech model from Alibaba, on a mobile CPU. The entry lists a vivo X300 with 8 CPU cores and 16 GB of memory, SME2, the XNNPACK and KleidiAI optimizations, FP16 weights and the LiteRT runtime. It reports a real-time factor of 1.2x against a baseline of 0.28x and a median end-to-end latency of 3,878 ms against 16,877 ms. Peak memory is 4,727 MB against 6,718 MB, and the evaluation uses the English subset of the MiniMaxAI TTS-Multilingual-Test-Set. Evaluation results in the Arm AI Portal, as shown in Arm's recap Credit: Arm Arm also points to Arm CSS for Mobile 2, which combines the Arm C2 CPU Cluster with SME2 and the Mali G2-Ultra NX GPU. Arm says the platform supports new on-device AI experiences on mobile. The next Arm Create event moves to the US, and Arm has not given a date. Source: https://newsroom.arm.com/blog/takeaways-from-arm-create-china-2026 Read the article: https://llmobile.news/ticker/arm-create-china-2026/ChipsAndroidTTShttps://llmobile.news/ticker/mediatek-dimensity-9600-pro/https://llmobile.news/ticker/mediatek-dimensity-9600-pro/Fri, 18 Sep 2026 17:55:18 +0200MediaTek announced the Dimensity 9600 Pro, a flagship smartphone chip built on a 2nm process. According to the company, its NPU 1090 supports on-device applications with models of up to 30B parameters. MediaTek reports 51% higher LLM prefill performance, the phase where the model reads the prompt, and 55% higher token generation per watt, measured on demo devices in its own labs. The chip pairs the NPU 1090 with a second-generation Super Efficient NPU, which MediaTek says cuts power consumption for always-on AI by 40%. The platform supports LPDDR6 memory and UFS 5.0 storage. In September 2025, MediaTek announced that it had completed the tape-out, the final design handoff to the fab, of a flagship chip on TSMC’s N2P 2nm process, with volume production expected in late 2026. The CPU uses a 2+3+3 layout of eight big cores, with two C2-Ultra cores at up to 4.55 GHz. MediaTek states up to 17% higher single-core and up to 15% higher multi-core performance over the previous generation, and up to 61% lower multi-core power consumption. The first smartphones with the Dimensity 9600 Pro and the related Dimensity 9600M are expected to launch this quarter, according to MediaTek. Source: https://www.mediatek.com/press-room/mediatek-dimensity-9600-pro-sets-new-standard-for-flagship-smartphone-chips Read the article: https://llmobile.news/ticker/mediatek-dimensity-9600-pro/ChipsAndroidhttps://llmobile.news/ticker/asus-ascent-qn10/https://llmobile.news/ticker/asus-ascent-qn10/Wed, 16 Sep 2026 00:00:00 +0200ASUS has announced the Ascent QN10, a mini PC built on the Snapdragon X2 Elite platform with an 18-core Qualcomm Oryon CPU and a Hexagon NPU rated at up to 80 TOPS. The company calls it the first AI mini PC with an 80 TOPS NPU and says it exceeds the Copilot+ PC requirements. The chassis measures under 0.7 liters, which ASUS puts at 86% smaller than a conventional 5-liter desktop, and the Adreno GPU is 2.3 times faster than in the previous generation. According to ASUS, the NPU is meant for local LLM inferencing, real-time translation, content generation, video enhancement and AI assistants. Developers can reach the Qualcomm AI Hub, which offers 175+ pre-optimized models and supports bringing their own models and data. The PC also runs agent frameworks such as OpenClaw and Hermes Agent, and ASUS describes a hybrid setup that routes workloads between cloud LLM APIs and the local NPU. Guru3d lists 16 GB or 32 GB of soldered LPDDR5X, two M.2 slots, Windows 11 on Arm and a 130 x 130 x 40 mm body, and reports that no price has been announced. The Gadgeteer names $1,349 for 16 GB with 512 GB of storage and $1,699 for 32 GB. Connectivity includes WiFi 7 and Bluetooth 6.0, and security comes from fTPM 2.0 and the Microsoft Pluton processor. Source: https://press.asus.com/news/press-releases/asus-ascent-qn10-mini-pc-snapdragon-x2-elite/ Read the article: https://llmobile.news/ticker/asus-ascent-qn10/ChipsNPUDeveloper toolshttps://llmobile.news/ticker/iphone-18-pro-a20-pro-neural-engine/https://llmobile.news/ticker/iphone-18-pro-a20-pro-neural-engine/Wed, 09 Sep 2026 19:00:00 +0200Apple has introduced the iPhone 18 Pro and iPhone 18 Pro Max with the A20 Pro chip. According to Apple, the chip has a new dual 16-core Neural Engine, 32 cores in total, which the company describes as double the AI processing power of A19 Pro. Apple says the Neural Engine accelerates on-device AI models and computational photography. Image: Apple. The A20 Pro also offers 50 percent more memory bandwidth than A19 Pro, and its 6-core CPU includes integrated Neural Accelerators. Apple positions the chip for “more advanced on-device AI workloads” alongside games. The phones ship with iOS 27, Apple Intelligence and the new Siri AI. Apple states that Apple Intelligence uses on-device processing together with Private Cloud Compute. Pre-orders start on 12 September, with availability from 18 September; prices start at $1,199 for the iPhone 18 Pro and $1,299 for the iPhone 18 Pro Max, both with 256 GB. Update, September 20, 2026. The retailer ZEERA reports results from a Max Tech side-by-side comparison of the iPhone 18 Pro Max and iPhone 17 Pro Max. Local LLM generation rose from 33.5 to 55.4 tok/s, a gain of 65 percent, and measured memory bandwidth from 66.5 to 111.8 GB/s, a gain of 68 percent. The comparison also lists 25 percent higher single-core and 29 percent higher multi-core CPU scores in Geekbench 7, and a 48 percent higher graphics score. Apple’s developer page for Apple Intelligence says the Foundation Models framework gives Swift apps direct access to the same on-device model that powers Apple Intelligence. New multimodal prompts pass images alongside text, and the model can call Vision framework tools such as OCR and barcode readers, all on-device according to Apple. Apps can also work with any model that conforms to the Language Model protocol, including cloud models like Claude and Gemini. Members of the App Store Small Business Program with fewer than 2 million first-time downloads get the next generation of Apple Foundation Models on Private Cloud Compute at no cloud API cost. The new Siri AI is a three-tier hybrid system, not fully on-device. A new System Orchestrator in iOS 27 routes every request to the right tier: Tier 1 — On-Device: Simple tasks (timers, app launches, local context search) run entirely on Apple’s Foundation Models (~3B parameters, 4-bit quantized) on the Neural Engine. Nothing leaves the iPhone. Tier 2 — Private Cloud Compute: Moderately complex requests route to Apple’s own servers on Apple Silicon (M2 Ultra, now M5) in hardware-isolated Secure Enclaves. Personal data is stripped and tokenized. Apple retains control; no data retention. Tier 3 — Google Gemini: The heaviest reasoning, real-time knowledge, and multimodal tasks are sent through PCC’s privacy proxy to a custom 1.2-trillion-parameter Gemini model on Nvidia Blackwell B200 GPUs in Google Cloud. Before any query reaches Google, the user’s identity and personal data are removed. Google is contractually barred from training on these queries. Apple reportedly pays Google ~$1 billion per year for this partnership. The System Orchestrator decides the routing threshold in real time based on task complexity and context size. Apple’s public materials only name On-Device and PCC as the two processing locations — Gemini is never mentioned on Apple’s consumer pages. Foundation Models can now work with any language model, including Apple’s own, Claude, and Gemini, through a single Swift interface. Apple did not publish details of the routing logic or which types of queries are sent off-device. Update, September 21, 2026. Adrien Grondin, who works on the Locally AI app, says on X that the iPhone 18 Pro runs a 27B model at double the speed of the iPhone 17 Pro. His 11-second video shows the demo, but the post names neither the model nor its quantization and gives no tok/s figures. Wccftech reports on the same demo, attributing it to Grondin and saying the model is Bonsai 2 27B from Prism ML — a ternary-weight version of Qwen3.8 27B at 1.76 bits per weight, 5.9 GB total. PrismML describes Bonsai 2 27B as released under Apache 2.0, running on Apple devices through MLX and on NVIDIA GPUs through CUDA. The iPhone 18 Pro is much better than what I expected for on-device AI It can run a 27B model at double the speed of the 17 Pro The new A20 Pro chip is a beast pic.twitter.com/gb11TvBfn0 — Adrien Grondin (@adrgrondin) September 19, 2026 Source: https://www.apple.com/newsroom/2026/09/apple-debuts-iphone-18-pro-and-iphone-18-pro-max/ Read the article: https://llmobile.news/ticker/iphone-18-pro-a20-pro-neural-engine/iPhoneChipsNPUhttps://llmobile.news/ticker/pixel-11-tensor-g6/https://llmobile.news/ticker/pixel-11-tensor-g6/Wed, 12 Aug 2026 19:00:00 +0200Google has announced the Pixel 11, Pixel 11 Pro and Pixel 11 Pro XL, built around the Tensor G6 chip. Google states that Tensor G6 packs 50 percent more TPU compute and, paired with the latest Gemini Nano model, processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy. The company also cites an upgraded CPU with 25 percent faster web browsing and 15 percent quicker app launches, and says the chip powers the 30x Super Zoom on the 5x telephoto lens. Google does not publish RAM figures, model sizes or per-task latency in the announcement. Pre-orders opened on 12 August, with retail availability from 20 August. ▶Meet Google Pixel 11 ProLoading connects your browser to www.youtube-nocookie.com, which may process your IP address and use cookies. Privacy details Load contentOpen externallyVideo: Made by Google. Source: https://blog.google/products-and-platforms/devices/pixel/google-pixel-11-pro-xl/ Read the article: https://llmobile.news/ticker/pixel-11-tensor-g6/ChipsNPUhttps://llmobile.news/ticker/a19-pro-neural-accelerators/https://llmobile.news/ticker/a19-pro-neural-accelerators/Tue, 09 Sep 2025 20:00:00 +0200Apple announced the A19 Pro alongside the iPhone 17 Pro on September 9, 2025. Its 6-core GPU carries Neural Accelerators built into each core, which Apple says work together with the 16-core Neural Engine to power AI models, graphics and games. The company states that the chip enables running large local language models on the phone. The A19 Pro also has a 6-core CPU that Apple calls the fastest in any smartphone, along with a larger cache and more memory than the A18 Pro. Combined with a vapor chamber cooling system, Apple puts sustained performance at up to 40 percent above the previous generation. Image: Apple. The vapor chamber Apple credits for the sustained performance gain. Source: https://www.apple.com/newsroom/2025/09/apple-unveils-iphone-17-pro-and-iphone-17-pro-max/ Read the article: https://llmobile.news/ticker/a19-pro-neural-accelerators/iPhoneChipsApple SiliconNPUhttps://llmobile.news/ticker/roma-qlora-accelerator/https://llmobile.news/ticker/roma-qlora-accelerator/Mon, 17 Mar 2025 10:44:00 +0100Researchers at Shanghai Jiao Tong University, Peking University and Microsoft Research Asia described ROMA on March 17, 2025, an accelerator design that holds a quantised language model in on-chip read-only memory. The paper reports results from Verilog synthesis against TSMC’s 7 nm standard cell library, not from a fabricated chip and not from an FPGA prototype, so every speed, area and power figure in it is a toolchain estimate rather than a measurement on hardware. On that basis the authors report peak decoding of 31,800 tok/s for a 4-bit 3B Llama model with an empty KV cache. The design splits storage by how often the weights change. The frozen base model, quantised to 2-bit or 4-bit, sits in ROM, which cannot be rewritten once the chip has been manufactured, while the small trainable LoRA adapter and the KV cache sit in SRAM, which can. The authors argue that a base model is stable enough for that, with updates expected over years rather than months, and that adaptation to new tasks happens in the adapter instead. What ROM buys is density, and the paper puts a ROM bit cell at roughly a third of the area of an SRAM bit cell in TSMC’s 7 nm memory compiler, enough to fit the whole quantised model on chip without external memory. The synthesised configuration carries 1.86 GB of ROM and 304 MB of SRAM at 500 MHz, with an area of 503.7 mm² and power of 33.1 W, the area and latency coming from Synopsys Design Compiler and the power from Synopsys PrimeTime PX. It holds either a 4-bit 3B or a 2-bit 8B Llama model entirely on chip, and for the 3B model with a rank-16 adapter the authors report a time to first token of 5.6 ms at 256 input tokens and 140.2 ms at 4K, with decoding staying above 10,000 tok/s once 4K tokens are cached. They also compare against measured hardware, an Intel i5-1135G7 running llama.cpp at 6.8 tok/s and an Nvidia RTX 4090 running TensorRT-LLM at 219 tok/s on the same 4-bit 3B model, against 20,078 tok/s for the ROMA estimate at a 256-token input. Most of the paper’s engineering goes into shrinking the ROM. A structure the authors call B-ROM stores the constant bits in the chip’s wiring instead of in transistors, which cuts the transistor count to about a quarter and the ROM area by around 40 percent against a standard ROM, and a fused cell layout places that wiring-heavy structure in the same physical area as the transistor-heavy compute logic. The paper states no tapeout, no fabrication schedule and no cost figures, and it names the fixed base model as the price of the approach, since ROM content is set at manufacture. It is posted under the arXiv perpetual non-exclusive license. Source: https://arxiv.org/abs/2503.12988 Read the article: https://llmobile.news/ticker/roma-qlora-accelerator/ChipsMemoryQuantisationResearchhttps://llmobile.news/ticker/genai-at-the-edge-survey/https://llmobile.news/ticker/genai-at-the-edge-survey/Wed, 19 Feb 2025 21:43:00 +0100Seven researchers at Johns Hopkins University and Duke University published a survey of generative AI on edge devices on February 19, 2025. Most of the accelerator hardware it collects has not been built. Its table of 12 accelerators for language and diffusion models covers 8 simulator studies against 4 fabricated chips, and the highest peak energy efficiency in it is 74.34 TOPS/W, from a 28nm computing-in-memory chip designed for Stable Diffusion. Compression is the part the survey treats as settled enough to quantify, and it attributes every figure to the work it reviews. It reports unstructured pruning reaching up to 60 percent sparsity on large models and a sparsity-aware inference system turning that into a 3 times speedup, while structured pruning that removes whole components gives about 2 times with little quality loss. Quantisation has been taken to 1 bit per weight in work such as BitNet, and the survey names what is still open there as holding generation quality under extreme compression and finding efficient ways to train quantised models on the edge devices themselves rather than only to run them. The frameworks chapter is where the survey names hardware a reader can buy. It cites a measurement that applying NVIDIA’s TensorRT to transformer models on a Jetson Xavier cuts latency by over 60 percent with negligible accuracy loss, and points to MELTing Point, a benchmark suite that tracks language model energy use and memory footprint across smartphones and Jetson boards. The authors state that no dedicated survey of generative AI at the edge existed before theirs, close by naming model personalisation and security across distributed edge nodes as the challenges that persist, and publish on arXiv under a Creative Commons Attribution 4.0 license. Diagram: Navardi and colleagues, from the survey. Source: https://arxiv.org/abs/2502.15816 Read the article: https://llmobile.news/ticker/genai-at-the-edge-survey/ResearchChipsQuantisationNPUhttps://llmobile.news/ticker/bitnet-b1-58/https://llmobile.news/ticker/bitnet-b1-58/Tue, 27 Feb 2024 19:56:00 +0100Microsoft Research and the University of Chinese Academy of Sciences published BitNet b1.58 on February 27, 2024, a language model in which every single weight is one of three values, -1, 0 or 1. At 3B parameters the authors measure it at 2.22 GB of memory against 7.89 GB for a full-precision Llama-style model of the same size trained on the same number of tokens, a 3.55 times reduction, with a slightly lower perplexity of 9.91 against 10.04. Three possible values need log2(3) bits to store, which is roughly 1.58 and where the name comes from. What that buys is a change to the matrix multiplication that dominates the work of running a model. A normal model multiplies each weight by an activation in floating point and sums the products, but multiplying by -1, 0 or 1 is only a sign flip, a skip or a copy, so the paper states that the matrix multiplication of BitNet “only involves integer addition”. Activations stay at 8 bits. The models are trained from scratch at this precision rather than trained in full precision and squeezed down afterwards, which is how most low-bit models on phones are produced today. The authors trained BitNet b1.58 and their own reproduced Llama baseline on the same data for the same number of tokens at each size, and compare the two directly. They report that BitNet b1.58 starts to match the full-precision baseline in perplexity at 3B and on zero-shot end tasks from 3B as well, where it averages 50.2 against 49.7. The efficiency figures widen with size. Memory drops 2.60 times at 700M, 2.93 times at 1.3B and 3.55 times at 3B, and latency per output token falls 1.23 times, 1.67 times and 2.71 times across the same three sizes. For throughput the authors ran 70B models on two A100 cards and report a batch size of 176 against 16 and 2977 tokens per second against 333, an 8.9 times gain. They also calculate that on 7nm chips the arithmetic for matrix multiplication costs 71.4 times less energy, because integer addition is far cheaper than floating-point multiply-accumulate. The paper names no model release and its arXiv listing marks it as work in progress. The authors argue the approach suits CPUs, “which are the main processors used in edge and mobile devices”, and say the lower memory and energy cost is what would let such models run there. They close by calling for new hardware and systems designed specifically for 1-bit models. Update, April 16, 2025. Microsoft released BitNet b1.58 2B4T, a 2B model trained from scratch on 4 trillion tokens at ternary precision, which the team calls the first open-source native 1-bit model at that scale. The report puts its non-embedding memory at 0.4 GB against 1.4 GB for Gemma-3 1B and 2.6 GB for Qwen2.5 1.5B, measures CPU decoding at 29 ms per token on a 13th Gen Intel Core i7-13800H using 8 threads against 41 ms and 65 ms for the same two models, and estimates energy at 0.028 J against 0.186 J and 0.347 J. Across the benchmark suite it averages 54.19, above Llama 3.2 1B at 44.90 and just under Qwen2.5 1.5B at 55.23. The weights are on Hugging Face, with a custom CUDA kernel for GPUs and CPU inference through bitnet.cpp, the runtime Microsoft published in October 2024 and measured at 2.37 to 6.17 times faster than the baseline on x86 CPUs and 1.37 to 5.07 times faster on ARM. Source: https://arxiv.org/abs/2402.17764 Read the article: https://llmobile.news/ticker/bitnet-b1-58/ResearchQuantisationMemoryChipshttps://llmobile.news/ticker/snapdragon-8-gen-3/https://llmobile.news/ticker/snapdragon-8-gen-3/Tue, 24 Oct 2023 19:00:00 +0200Qualcomm launched the Snapdragon 8 Gen 3 at its Snapdragon Summit in Hawaii on October 24, 2023, calling it its first mobile platform designed with generative AI in mind. On the product page the company states support for generative models with up to 10 billion parameters on device and up to 20 tokens per second for large language models. Qualcomm puts the Hexagon NPU at 98 percent faster than the previous generation and claims 40 percent better performance per watt for sustained AI inference. It lists the Kryo CPU at 30 percent more performance and 20 percent better power efficiency, and the Adreno GPU at 25 percent faster rendering with 25 percent better efficiency. Among the workloads Qualcomm names for local execution are Stable Diffusion, virtual assistants and chatbots. Devices were announced by ASUS, Honor, iQOO, MEIZU, Nubia, OnePlus, OPPO, realme, Redmi, RedMagic, Sony, vivo, Xiaomi and ZTE. Image: Qualcomm. Source: https://www.qualcomm.com/news/releases/2023/10/qualcomm-launches-premium-snapdragon-8-gen-3-to-bring-generative Read the article: https://llmobile.news/ticker/snapdragon-8-gen-3/ChipsNPUAndroid